Accelerated Static Compaction for Sequential Circuits by Exploiting "Essential" Subsequences
نویسندگان
چکیده
In this paper a GA-based method that compacts Test Sequences for sequential circuits is presented. In this algorithm from an initial set of test sequences a subset of sequences is selected and from these sequences parts of them (subsequences) are selected which are reordered and combined into one sequence covering all faults detected by the initial set. The method exploits the presence of essential sequences in the set to reduce the search space, thus easing the work of the GA. Experimental results support the usefulness of the proposed method. Key-Words: Sequential Digital Circuits, Sequence Compaction, Test Generation, Genetic Algorithms.
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